Cheetah  Framework for fpga algo trading

Building your trading solution in FPGAs can provide orders of magnitude reduction in tick-to-trade latency. But with your alg in FPGA, its not so easy to tweak. Even a small change can cause a week of headaches for your FPGA development team.

CheetahFramework allows you to change and tweak your FPGA based Algo without having to recode it.

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  • Overview
  • Example
  • Algo Module
  • Framework API

Diagram showing Cheetah Framework IP Cores providing services to hardware trading appliance

Cheetah Framework helps you create on-the-fly reconfigurable FPGA designs by providing a complete framework for runtime recofigurable routing, parameter configuration, status reporting, and auditing in FPGA trading systems.

By splitting your Alg up into functional modules, you can decide at runtime how these should be interconnected. Once you've coded the initial set of modules, it's like playing with Lego blocks.

The Cheetah Framework Encapsulates your Alg's modules and provides hardware support for runtime configurable event routing, lookup bus interconnect and arbitration, host configuration stream decoding, and status & audit encoding for transmission to host.

Instead of hard coding your Alg, the Framework's Router component, can dynamically connect and reconnect any of your Alg's modules to any other through configuration commands from the host server.

The Lookup Bus provides an arbitrated interconnect to allow any module to get instrument specific data from any other module that provides it.

The Status Sender encodes Alg module status as well as audit logs from the Router and Lookup Bus into a byte stream that can be transmitted to a host server over paths such as IP or PCIe.

The Config block takes data that has been received from a host server and deserialises it to drive a configuration bus which can be used to configure your Alg's modules and Cheetah Framework components.

Example of an fpga algo trading configuration

This example shows how Algo Modules can be wired together to make a simple algo trading engine. In this case, the input events are price ticks from a market feed. The feed into two blocks: MACD and HLOC.

MACD looks at the crossing of two different length moving average, and could be configured to look for a 1ms moving average crossing a 10ms moving average, for example.

HLOC derives periodic high, low, open, and close metrics on the price. It drives the ATR block which derives a sense of trend strength (in order to do this, ATR looks up high, low, and close information from the HLOC block over the lookup bus).

Both MACD and ATR feed into the Logic block which compares MACD and ATR against constants. If they are both greater than configurable values, Logic Block sends out a buy signal.

All of this processing is fully pipelined and can operate on up to 255 instruments in parallel.

Example of a MACD fpga IP Core for algo trading

In the context of the Cheetah Framework, an Algo Module is a self-contained FPGA block that processes price or volume ticks. This example shows a MACD block which processes price ticks and produces three outputs according to the MACD specification.

You can fit any algo module into the framework, provided it supports the Cheetah Framework interface.

Cheetah Cub IP Cores provide building blocks to help you get your Algo Module up and running fast. You can also use our Cheetah Blocks which are complete Algo Modules with specific functions.

An Algo Module interfaces into the Cheetah Framework through the following hardware APIs:

Input Events: price or volume ticks on a specified instrument. Up to 255 instruments can be selected.

Output Events: Output ticks on a specified instrument.

Config: Configuration and Commands for run-time setting of parameters and sending operational commands to the Algo Module.

Status: Request and response port for reading status information from the Algo Module.

Realtime Clock: Clock ticks for the Algo Module to use if desired.

Lookup Service: The Algo Module may provide a service to expose statistical instrument data that it has calculated.

Lookup Request: The Algo Module may request statistical instrument data from another Algo Module.

 

Deliverables:

VHDL Source (site license)

Self Checking Testbench

Documentation

Reference Design

Support


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Patent Pending 61739845