Cheetah Blocks provide ready IP Cores for EMA, ADX, ATR for fpga algo trading

Optimised solutions to bring you to the market faster. Cheetah Blocks provide ready to use functionality for extracting Technical Indicator data such as MACD, ADX, and more, from Market Data or other event based data.

Pipelined designs operate with as many as 255 instruments in parallel (per IP Core instantiation) with high throughput and low latency.



  • Overview
  • Example
  • Timing
MACD IP Core for fpag algo trading

A Cheetah Block is an IP core that essentially processes data events on one or more inputs and produces output events on one or more outputs. A configuration port allows configuration of block parameters such as moving average coefficients. Commands can also be sent to the block to modify its behaviour in realtime.

It is also possible to have the block transmit its status (internal state, event counter, etc) on a status bus.

Some blocks provide a lookup port which allows other blocks to do asynchronous lookups of computed data (such as highs, lows, ATR values). Some blocks use such services to obtain instrument data from other blocks (for example, the ATR block needs access to market high and low data).

This example shows how Cheetah Blocks can be wired together to make a simple algo trading engine. In this case, the input events are price ticks from a market feed. The feed into two blocks: MACD and HLOC.

MACD looks at the crossing of two different length moving average, and could be configured to look for a 1ms moving average crossing a 10ms moving average, for example.

HLOC derives periodic high, low, open, and close metrics on the price. It drives the ATR block which derives a sense of trend strength (in order to do this, ATR looks up high, low, and close information from the HLOC block over the lookup bus).

Both MACD and ATR feed into the Logic block which compares MACD and ATR against constants. If they are both greater than configurable values, Logic Block sends out a buy signal.

All of this processing is fully pipelined and can operate on up to 255 instruments in parallel.

This diagram shows the timing of the MACD Cheetah Block. In this scenario it has received a single input event at 0ns and gives a MACD output at 188ns.

Because the design is pipelined, it can receive new events on other instruments (not shown on this diagram) while it is processing the first (and others).

If another input event arrives on an instrument that is already being processed in the pipeline, the input blocks until the pipeline is clear for that instrument.


VHDL Source (site license)

Self Checking Testbench


Java simulator



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Patent Pending 61739845